Field of the Invention
The invention relates to a read-only memory cell array and a method for producing the memory cell. In semiconductor technology, read-only memories (ROM) can be implemented by a memory cell array in which the individual memory cells essentially include vertical MOS transistors in a semiconductor substrate. When the memory cell configuration is read out, the individual memory cells are selected via a word line. The gate electrode of the MOS transistors is in each case connected to the word line. The input of each MOS transistor is connected to a reference line, and the output to a bit line. During the reading procedure, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned as a function of this. Technically, the zero and one values are stored in the read-only memory by virtue of the fact that, in memory cells in which the logic value assigned results in "no current flow through the transistor", neither a MOS transistor nor a connective connection to the bit line is produced. Alternatively, the two logic values can be implemented by MOS transistors which have different threshold voltages owing to different implantations in the channel area. Such memory cells are described in detail in German Patents DE 195 14 834 C1 and DE 44 37 581 C2, for example.
In the known fabricating methods, vertically disposed doped areas to be produced in the semiconductor substrate are used to form the vertical MOS transistors. Long trenches which extend in parallel are etched into the semiconductor substrate and are filled with an insulation material. Strip-shaped, doped regions which are oppositely doped to the semiconductor substrate form a bit line used to read out the memory cell or as a reference line which can be disposed on the base and/or on the substrate surface.
At points at which the MOS transistor is to be formed (the corresponding cells are referred to below, as in the quoted patent documents, as "first memory cells"), a suitable etching mask (so-called programming mask) is used to etch a hole into the first insulation material in the trench. The hole exposes the trench wall assigned to the first memory cell. At the other points, that is to say in the region of second memory cells which do not have a MOS transistor, and in the region between two memory cells which are adjacent in the direction of the trench, no hole is etched. In other words, the trench remains filled with the first insulation material. Then, a gate oxide is produced in the hole, and polysilicon, for example, is deposited and structured to form word lines, where the word lines run transversely with respect to the trenches. The word line here covers the gate oxide on the trench wall and thus forms the gate of the first memory cell. More details on the fabrication methods are described in the above-mentioned patent documents.
In the conventional fabrication methods, the following problems arise:
First, when the trench is filled with the insulating material, so-called shrinkage cavities may arise. These are porous weak points or holes which are produced approximately in the center of the trench as a growth joint if the deposited layer thickness is precisely half the width of the trench. As the trench fills up, the shrinkage cavities are buried. If the hole is subsequently etched using the programming mask to produce the transistor, the shrinkage cavity is opened at the sides, and, during the later deposition of the word-line material, the shrinkage cavity is filled with this conductive material, that is to say for example polysilicon to form the word lines. The buried polysilicon stringer cannot be removed during the structuring of the polysilicon into word lines. As a result, a short-circuit is produced between adjacent word lines, that is to say in particular between adjacent first memory cells.
Second, in order to ensure a reliable overlap of a word line and a programming hole in the event of alignment errors of the word line mask with respect to the programming mask, it is necessary in the conventional methods to select the width of the word lines to be greater than the width of the holes. As a rule of thumb, an alignment error of 1/3 F is to be calculated for a structure size F which has the minimum possible resolution, so that the width of the word lines must be 5/3 F. Since the word-line spacing must be at least F, the word line grid spacing is increased to 22/3 F.